1. Field of the Invention
The present invention relates to a semiconductor device having an electrostatic discharge (ESD) protection element disposed between an external connection terminal and an internal circuit region in order to protect internal elements formed in the internal circuit region from breakdown due to ESD.
2. Description of the Related Art
In a semiconductor device including MOS transistors, an off transistor, which is an NMOS transistor provided in an off-state whose gate potential is fixed to the ground potential (Vss), is used as an ESD protection element for preventing breakdown of an internal circuit due to static electricity supplied from a pad provided for external connection.
In order to avoid the ESD breakdown of the internal elements, it is important to draw a large portion of an electrostatic pulse as much as possible into the off transistor to prevent propagation of the electrostatic pulse to the internal elements, or to change a fast and large electrostatic pulse into a slow and small signal before passing to the internal elements.
Since the off transistor must flow a large amount of current generated by static electricity at once unlike ordinary MOS transistors forming the internal circuit such as a logic circuit, a large width (width W) of about several hundred micrometers is required for the transistor in many cases.
Accordingly, the off transistor often takes a form which is obtained by combining a plurality of drain regions, source regions, and gate electrodes in a comb shape. However, the structure in which a plurality of transistors is combined causes the difficulty in uniformly operating the whole NMOS transistors for ESD protection. For example, current concentration occurs in a portion closer to the external connection terminal, resulting in the breakdown of the off transistor without sufficiently exhibiting the original ESD protection function.
As countermeasures, there is proposed a method in which a distance between a contact hole formed on a drain region and a gate electrode is made smaller to accelerate the operation of the transistor as a distance from the external connection terminal becomes longer (for example, refer to FIG. 2 of JP 7-45829 A).
However, when a width W is made smaller for uniform operation of the off transistor, the protection function is not sufficiently accomplished. Further, in the method of JP 7-45829 A, the distance between the contact and the gate electrode in the drain region is adjusted to thereby locally adjust a transistor operation speed. The method, however, has problems that a desired contact position cannot be ensured along with a reduction in width of the drain region, that interconnect resistance has been made low through interconnect including a refractory metal in recent years to thereby accelerate the propagation speed of surge, which causes a case where the transistor operation speed cannot be adjusted only by the distance between the contact and the gate electrode, and that it is difficult to adapt the method to a case in which interconnect to the transistor is introduced from a direction perpendicular to the width direction of the transistor. Further, in JP 7-45829 A, there is not disclosed a method for drawing a large portion of an electrostatic pulse as much as possible into the off transistor to prevent propagation of the electrostatic pulse to the internal elements, or a method for changing a fast and large electrostatic pulse into a slow and small signal before passing to the internal elements, in order to avoid the ESD breakdown of the internal elements.